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INDEX
- What is XSCHEM
- Install XSCHEM
- Run XSCHEM
- XSCHEM elements
- Symbols
- XSCHEM properties
- Component instantiation
- Symbol properties syntax
- Component properties syntax
- Creating a circuit schematic
- Creating symbols
- Component parameters
- More info on creating a parametric subcircuit
- Editor commands
- Netlisting
- Net Probes
- Simulation
- Viewing simulation data with XSCHEM
- Developer Info, XSCHEM file format specification
- XSCHEM remote interface specification
TUTORIALS
- Step by step instructions: Install XSCHEM
- Run a simulation with XSCHEM
- Create a symbol and use an existing subcircuit netlist
- Instance based selection of symbol implementation
- Symbol and Schematic generators (aka Pcells)
- Create a symbol with XSCHEM
- Manage XSCHEM design libraries / symbol librares
- Use bus / vector notation for signal bundles / arrays of instances
- Backannotation of Ngspice simulation data into xschem
- Use symgen.awk to create symbols from 'djboxsym' compatible text files
- Translate GEDA gschem/lepton-schematic schematics and symbols to xschem.
- Xschem Google-Skywater 130n (Sky130) process integration
- [Video] Install Xschem, Xschem_sky130, skywater-pdk and ngspice: step by step instructions
- [Video] Second version, Install Xschem and open_pdks for skywater 130 design
- [Video] Editing commands and simulation
- [Video] Work on different projects in one running Xschem instance
- [Video] Editing component attributes
- [Video] Copying objects across xschem windows
- [Video] Symbols with inherited connections
- [Video] Search / replace function
- [Video] Visualize differences between two schematics with xschem
- [Video] How to stretch objects
- [Video] Parameters in subcircuits
- [Video] Create pins from net labels, fix grid align issues, wires
- [Video] Link documentation to components/symbols
- [Video] Use rawtovcd to show ngspice waveforms in gtkwave
- [Video] Run a Verilog simulation with XSCHEM and icarus Verilog
- [Video] See logic propagation of nets live in xschem without using a backend simulator
- [Video] View Ngspice/Xyce simulation data inside XSCHEM
- [Video] Live annotation of simulation values into the schematic
- [Video] Setting up a Xyce simulation, viewing results and doing math on graphs
- [Video] Probe xschem nets into the GAW waveform viewer
- [Video] Probe xschem nets into the BESPICE waveform viewer
- [Video] Creating a symbol
- [Video] Instantiating schematics instead of symbols (LCC, Local Custom Cell)
- [Video] Using more schematic views of a symbol to do simulation at different abstraction levels
- [Video] Let components display the name of the net attached to their pins
- [Video] New editing commands on shapes, polygons and bezier curves.
- [Video] New user friendly 'click and drag' interface
- [Video] Simulate the same circuit with different simulators, SPICE, Verilog, VHDL
- [Video] Ngspice / Verilog-A cosimulation
FAQ