FEATURE | DESCRIPTION |
Bus notation for nets and components. | Yes. |
Portability. | All UNIX systems with Tcl and X11, Windows with VS and Active-Tcl. |
Netlisting performance. | Extremely fast, Complex system with 59 sub blocks netlisted in VHDL in < 1 second on a Linux laptop. |
Primitive component creation with arbitrary code for VHDL/SPICE/verilog. | Works out of the box with very simple property strings. |
Single / split file netlisting. | Yes, any supported netlist formats. |
Mixed mode netlisting, symbol based. | Yes, in split netlisting mode. |
Automatic symbol creation from schematic and vice-versa. | Yes. |
Property editing on multiple instances, changing only modified token/value pairs, even on different symbol sets. | Yes. |
Pin creation from schematic nets. | Yes, net names can be changed to pins and vice-versa, function to automatically generate pins for nets that are undriven. |